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-rw-r--r--src/arch/arm/isa.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0df50a85e..ee2799147 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
fpscrMask.n = ones;
newVal = (newVal & (uint32_t)fpscrMask) |
(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
- tc->getDecodePtr()->setContext(newVal);
+ tc->getDecoderPtr()->setContext(newVal);
}
break;
case MISCREG_CPSR_Q: