1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 67062be41..87203c3f0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -173,11 +173,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         cpsr.t = pc.thumb() ? 1 : 0;
         return cpsr;
     }
-    if (misc_reg >= MISCREG_CP15_UNIMP_START &&
-        misc_reg < MISCREG_CP15_END) {
+    if (misc_reg >= MISCREG_CP15_UNIMP_START)
         panic("Unimplemented CP15 register %s read.\n",
               miscRegName[misc_reg]);
-    }
+
     switch (misc_reg) {
       case MISCREG_CLIDR:
         warn_once("The clidr register always reports 0 caches.\n");