diff options
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 216ae04e7..9988d431a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -447,6 +447,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) default: panic("Security Extensions not implemented!"); } + warn("Translating via MISCREG in atomic mode! Fix Me!\n"); req->setVirt(0, val, 1, flags, tc->pcState().pc()); fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); if (fault == NoFault) { @@ -475,7 +476,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tc->getITBPtr()->invalidateMiscReg(); tc->getDTBPtr()->invalidateMiscReg(); break; - + case MISCREG_CPSR_MODE: + // This miscreg is used by copy*Regs to set the CPSR mode + // without updating other CPSR variables. It's used to + // make sure the register map is in such a state that we can + // see all of the registers for the copy. + updateRegMap(val); + return; } } setMiscRegNoEffect(misc_reg, newVal); |