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-rw-r--r--src/arch/arm/isa.hh16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index e05f0e18a..8de90dc93 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -177,6 +177,22 @@ namespace ArmISA
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ }
+ return RegId();
+ }
+
int
flattenIntIndex(int reg) const
{