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-rw-r--r--src/arch/arm/isa.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1d8f14cab..f6ad56dd4 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -168,6 +168,10 @@ namespace ArmISA
case MISCREG_CLIDR:
warn("The clidr register always reports 0 caches.\n");
break;
+ case MISCREG_CCSIDR:
+ warn("The ccsidr register isn't implemented and "
+ "always reads as 0.\n");
+ break;
}
return readMiscRegNoEffect(misc_reg);
}
@@ -235,6 +239,9 @@ namespace ArmISA
panic("Disabling coprocessors isn't implemented.\n");
}
break;
+ case MISCREG_CSSELR:
+ warn("The csselr register isn't implemented.\n");
+ break;
}
return setMiscRegNoEffect(misc_reg, newVal);
}