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-rw-r--r--src/arch/arm/isa.hh12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1931306f9..b4689d74e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -105,6 +105,8 @@ namespace ArmISA
*/
bool impdefAsNop;
+ bool afterStartup;
+
/** MiscReg metadata **/
struct MiscRegLUTEntry {
uint32_t lower; // Lower half mapped to this register
@@ -706,6 +708,16 @@ namespace ArmISA
Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
+ /** Getter for haveGICv3CPUInterface */
+ bool haveGICv3CpuIfc() const
+ {
+ // haveGICv3CPUInterface is initialized at startup time, hence
+ // trying to read its value before the startup stage will lead
+ // to an error
+ assert(afterStartup);
+ return haveGICv3CPUInterface;
+ }
+
Enums::VecRegRenameMode
vecRegRenameMode() const
{