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-rw-r--r--src/arch/arm/isa/decoder.isa3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index b84109546..8b4175f9c 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -830,8 +830,7 @@ decode COND_CODE default Unknown::unknown() {
}
format PredOp {
// ARM System Call (SoftWare Interrupt)
- 1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
- condCode))
+ 1: swi({{ if (testPredicate(Cpsr, condCode))
{
//xc->syscall(R7);
xc->syscall(IMMED_23_0);