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-rw-r--r--src/arch/arm/isa/decoder.isa294
1 files changed, 13 insertions, 281 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 623b2415d..76d584858 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -37,47 +37,8 @@
// in the ARM ISA specification document starting with Table B.1 or 3-1
//
//
-decode COND_CODE default Unknown::unknown() {
- 0xf: decode COND_CODE {
- 0x0: decode OPCODE {
- // Just a simple trick to allow us to specify our new uops here
- 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }},
- 'IsMicroop');
- 0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }},
- 'IsMicroop');
- 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
- {{ EA = Raddr + disp; }},
- inst_flags = [IsMicroop]);
- 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
- {{ EA = Raddr + disp; }},
- inst_flags = [IsMicroop]);
- 0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }},
- 'IsMicroop');
- 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }},
- 'IsMicroop');
- }
- 0x1: decode OPCODE {
- 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
- 'IsMicroop');
- 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
- Rlo = Fd.ud & 0xffffffff; }},
- 'IsMicroop');
- 0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }},
- {{ EA = Rn + disp; }},
- inst_flags = [IsMicroop]);
- 0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }},
- {{ EA = Rn + disp; }},
- inst_flags = [IsMicroop]);
- 0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }},
- {{ EA = Rn + disp; }},
- inst_flags = [IsMicroop]);
- 0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }},
- {{ EA = Rn + disp; }},
- inst_flags = [IsMicroop]);
- }
- default: Unknown::unknown(); // TODO: Ignore other NV space for now
- }
-default: decode ENCODING {
+
+decode ENCODING default Unknown::unknown() {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
@@ -112,145 +73,15 @@ format DataOp {
0x19: WarnUnimpl::ldrex();
}
}
- 0xb: decode PUBWL {
- format ArmStoreMemory {
- 0x0: strh_({{ Mem.uh = Rd;
- Rn = Rn - Rm; }},
- {{ EA = Rn; }});
- 0x4: strh_i({{ Mem.uh = Rd;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x8: strh_u({{ Mem.uh = Rd;
- Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0xc: strh_ui({{ Mem.uh = Rd;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x10: strh_p({{ Mem.uh = Rd; }},
- {{ EA = Rn - Rm; }});
- 0x12: strh_pw({{ Mem.uh = Rd;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
- 0x14: strh_pi({{ Mem.uh = Rd.uh; }},
- {{ EA = Rn + hilo; }});
- 0x16: strh_piw({{ Mem.uh = Rd;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- 0x18: strh_pu({{ Mem.uh = Rd; }},
- {{ EA = Rn + Rm; }});
- 0x1a: strh_puw({{ Mem.uh = Rd;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x1c: strh_pui({{ Mem.uh = Rd; }},
- {{ EA = Rn + hilo; }});
- 0x1e: strh_puiw({{ Mem.uh = Rd;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- }
- format ArmLoadMemory {
- 0x1: ldrh_l({{ Rd = Mem.uh;
- Rn = Rn - Rm; }},
- {{ EA = Rn; }});
- 0x5: ldrh_il({{ Rd = Mem.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x9: ldrh_ul({{ Rd = Mem.uh;
- Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0xd: ldrh_uil({{ Rd = Mem.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x11: ldrh_pl({{ Rd = Mem.uh; }},
- {{ EA = Rn - Rm; }});
- 0x13: ldrh_pwl({{ Rd = Mem.uh;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
- 0x15: ldrh_pil({{ Rd = Mem.uh; }},
- {{ EA = Rn + hilo; }});
- 0x17: ldrh_piwl({{ Rd = Mem.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- 0x19: ldrh_pul({{ Rd = Mem.uh; }},
- {{ EA = Rn + Rm; }});
- 0x1b: ldrh_puwl({{ Rd = Mem.uh;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x1d: ldrh_puil({{ Rd = Mem.uh; }},
- {{ EA = Rn + hilo; }});
- 0x1f: ldrh_puiwl({{ Rd = Mem.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- }
- }
- format ArmLoadMemory {
- 0xd: decode PUBWL {
- 0x1: ldrsb_l({{ Rd = Mem.sb;
- Rn = Rn - Rm; }},
- {{ EA = Rn; }});
- 0x5: ldrsb_il({{ Rd = Mem.sb;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x9: ldrsb_ul({{ Rd = Mem.sb;
- Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0xd: ldrsb_uil({{ Rd = Mem.sb;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x11: ldrsb_pl({{ Rd = Mem.sb; }},
- {{ EA = Rn - Rm; }});
- 0x13: ldrsb_pwl({{ Rd = Mem.sb;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
- 0x15: ldrsb_pil({{ Rd = Mem.sb; }},
- {{ EA = Rn + hilo; }});
- 0x17: ldrsb_piwl({{ Rd = Mem.sb;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- 0x19: ldrsb_pul({{ Rd = Mem.sb; }},
- {{ EA = Rn + Rm; }});
- 0x1b: ldrsb_puwl({{ Rd = Mem.sb;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x1d: ldrsb_puil({{ Rd = Mem.sb; }},
- {{ EA = Rn + hilo; }});
- 0x1f: ldrsb_puiwl({{ Rd = Mem.sb;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- }
- 0xf: decode PUBWL {
- 0x1: ldrsh_l({{ Rd = Mem.sh;
- Rn = Rn - Rm; }},
- {{ EA = Rn; }});
- 0x5: ldrsh_il({{ Rd = Mem.sh;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x9: ldrsh_ul({{ Rd = Mem.sh;
- Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0xd: ldrsh_uil({{ Rd = Mem.sh;
- Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x11: ldrsh_pl({{ Rd = Mem.sh; }},
- {{ EA = Rn - Rm; }});
- 0x13: ldrsh_pwl({{ Rd = Mem.sh;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
- 0x15: ldrsh_pil({{ Rd = Mem.sh; }},
- {{ EA = Rn + hilo; }});
- 0x17: ldrsh_piwl({{ Rd = Mem.sh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- 0x19: ldrsh_pul({{ Rd = Mem.sh; }},
- {{ EA = Rn + Rm; }});
- 0x1b: ldrsh_puwl({{ Rd = Mem.sh;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x1d: ldrsh_puil({{ Rd = Mem.sh; }},
- {{ EA = Rn + hilo; }});
- 0x1f: ldrsh_puiwl({{ Rd = Mem.sh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
- }
+ format AddrMode3 {
+ 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
+ load, {{ Rd = Mem.uh; }});
+ 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32); }},
+ load, {{ Rd = Mem.sb; }});
+ 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
+ (Rdo.ud << 32); }},
+ load, {{ Rd = Mem.sh; }});
}
}
0: decode IS_MISC {
@@ -355,107 +186,9 @@ format DataOp {
0xb: WarnUnimpl::mrs_i_spsr();
}
}
- 0x2: decode PUBWL {
- // CAREFUL:
- // Can always do EA + disp, since we negate disp using the UP flag
- // Post-indexed variants
- 0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd;
- Rn = Rn + disp; }},
- {{ EA = Rn; }});
- 0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp;
- Rd = Mem; }},
- {{ EA = Rn; }});
- 0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub;
- Rn = Rn + disp; }},
- {{ EA = Rn; }});
- 0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp;
- Rd.ub = Mem.ub; }},
- {{ EA = Rn; }});
- // Pre-indexed variants
- 0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }});
- 0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }});
- 0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd;
- Rn = Rn + disp; }});
- 0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp;
- Rd = Mem; }});
- 0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }});
- 0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }});
- 0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub;
- Rn = Rn + disp; }});
- 0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp;
- Rd.ub = Mem.ub; }});
- }
+ 0x2: AddrMode2::addrMode2(Disp, disp);
0x3: decode OPCODE_4 {
- 0: decode PUBWL {
- format ArmStoreMemory {
- 0x00, 0x02: strr_({{ Mem = Rd;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn; }});
- 0x04, 0x06: strr_b({{ Mem = Rd.ub;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn; }});
- 0x08, 0x0a: strr_u({{ Mem = Rd;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn; }});
- 0x0c, 0x0e: strr_ub({{ Mem.ub = Rd.ub;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn; }});
- 0x10: strr_p({{ Mem = Rd; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x12: strr_pw({{ Mem = Rd;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x14: strr_pb({{ Mem.ub = Rd.ub; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x16: strr_pbw({{ Mem.ub = Rd.ub;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x18: strr_pu({{ Mem = Rd; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1a: strr_puw({{ Mem = Rd;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1c: strr_pub({{ Mem.ub = Rd; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1e: strr_pubw({{ Mem.ub = Rd;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn + Rm_Imm; }});
- }
- format ArmLoadMemory {
- 0x01,0x03: ldrr_l({{ Rd = Mem;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn; }});
- 0x05,0x07: ldrr_bl({{ Rd = Mem.ub;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn; }});
- 0x09,0x0b: ldrr_ul({{ Rd = Mem;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn; }});
- 0x0d,0x0f: ldrr_ubl({{ Rd = Mem.ub;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn; }});
- 0x11: ldrr_pl({{ Rd = Mem; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x13: ldrr_pwl({{ Rd = Mem;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x15: ldrr_pbl({{ Rd = Mem.ub; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x17: ldrr_pbwl({{ Rd = Mem.ub;
- Rn = Rn - Rm_Imm; }},
- {{ EA = Rn - Rm_Imm; }});
- 0x19: ldrr_pul({{ Rd = Mem; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1b: ldrr_puwl({{ Rd = Mem;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1d: ldrr_publ({{ Rd = Mem.ub; }},
- {{ EA = Rn + Rm_Imm; }});
- 0x1f: ldrr_pubwl({{ Rd = Mem.ub;
- Rn = Rn + Rm_Imm; }},
- {{ EA = Rn + Rm_Imm; }});
- }
- }
+ 0: AddrMode2::addrMode2(Shift, Rm_Imm);
1: decode MEDIA_OPCODE {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
0x8: decode MISC_OPCODE {
@@ -696,5 +429,4 @@ format DataOp {
}
}
}
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 06:30:07 +0000