diff options
Diffstat (limited to 'src/arch/arm/isa/decoder/arm.isa')
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 34 |
1 files changed, 1 insertions, 33 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 58b9f6699..f1fb57fc1 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -71,39 +71,7 @@ format DataOp { 0: ArmDataProcReg::armDataProcReg(); 1: decode OPCODE_7 { 0x0: decode MISC_OPCODE { - 0x0: decode OPCODE { - 0x8: PredOp::mrs_cpsr({{ - Rd = (Cpsr | CondCodes) & 0xF8FF03DF; - }}); - 0x9: decode USEIMM { - // The mask field is the same as the RN index. - 0: PredOp::msr_cpsr_reg({{ - uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodes, - Rm, RN, false); - Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; - }}); - 1: PredImmOp::msr_cpsr_imm({{ - uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodes, - rotated_imm, RN, false); - Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; - }}); - } - 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); - 0xb: decode USEIMM { - // The mask field is the same as the RN index. - 0: PredOp::msr_spsr_reg({{ - Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); - }}); - 1: PredImmOp::msr_spsr_imm({{ - Spsr = spsrWriteByInstr(Spsr, rotated_imm, - RN, false); - }}); - } - } + 0x0: ArmMsrMrs::armMsrMrs(); 0x1: decode OPCODE { 0x9: ArmBx::armBx(); 0xb: PredOp::clz({{ |