diff options
Diffstat (limited to 'src/arch/arm/isa/decoder/arm.isa')
-rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 1154bd0ba..dcdce6ca2 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -314,71 +314,6 @@ format DataOp { 1: Branch::bl({{ }}, Link); } 0x6: decode CPNUM { - 0x1: decode PUNWL { - 0x02,0x0a: decode OPCODE_15 { - 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; - Rn = Rn + disp8; }}, - {{ EA = Rn; }}); - 1: ArmMacroFPAOp::stfd_({{ }}); - } - 0x03,0x0b: decode OPCODE_15 { - 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; - Rn = Rn + disp8; }}, - {{ EA = Rn; }}); - 1: ArmMacroFPAOp::ldfd_({{ }}); - } - 0x06,0x0e: decode OPCODE_15 { - 0: ArmMacroFPAOp::stfe_nw({{ }}); - } - 0x07,0x0f: decode OPCODE_15 { - 0: ArmMacroFPAOp::ldfe_nw({{ }}); - } - 0x10,0x18: decode OPCODE_15 { - 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, - {{ EA = Rn + disp8; }}); - 1: ArmMacroFPAOp::stfd_p({{ }}); - } - 0x11,0x19: decode OPCODE_15 { - 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, - {{ EA = Rn + disp8; }}); - 1: ArmMacroFPAOp::ldfd_p({{ }}); - } - 0x12,0x1a: decode OPCODE_15 { - 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; - Rn = Rn + disp8; }}, - {{ EA = Rn + disp8; }}); - 1: ArmMacroFPAOp::stfd_pw({{ }}); - } - 0x13,0x1b: decode OPCODE_15 { - 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; - Rn = Rn + disp8; }}, - {{ EA = Rn + disp8; }}); - 1: ArmMacroFPAOp::ldfd_pw({{ }}); - } - 0x14,0x1c: decode OPCODE_15 { - 0: ArmMacroFPAOp::stfe_pn({{ }}); - } - 0x15,0x1d: decode OPCODE_15 { - 0: ArmMacroFPAOp::ldfe_pn({{ }}); - } - 0x16,0x1e: decode OPCODE_15 { - 0: ArmMacroFPAOp::stfe_pnw({{ }}); - } - 0x17,0x1f: decode OPCODE_15 { - 0: ArmMacroFPAOp::ldfe_pnw({{ }}); - } - } - 0x2: decode PUNWL { - // could really just decode as a single instruction - 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); - 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); - 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); - 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); - 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); - 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); - 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); - 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); - } 0xb: decode LOADOP { 0x0: WarnUnimpl::fstmx(); 0x1: WarnUnimpl::fldmx(); |