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Diffstat (limited to 'src/arch/arm/isa/formats/m5ops.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/m5ops.isa | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa new file mode 100644 index 000000000..2f5fe2c3a --- /dev/null +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -0,0 +1,78 @@ +// +// Copyright (c) 2010 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gene Wu +/// + +def format M5ops() {{ + decode_block = ''' + { + const uint32_t m5func = bits(machInst, 23, 16); + switch(m5func) { +#if FULL_SYSTEM + case 0x00: return new Arm(machInst); + case 0x01: return new Quiesce(machInst); + case 0x02: return new QuiesceNs(machInst); + case 0x03: return new QuiesceCycles(machInst); + case 0x04: return new QuiesceTime(machInst); +#endif + case 0x07: return new Rpns(machInst); + case 0x09: return new WakeCPU(machInst); + case 0x10: return new Deprecated_ivlb(machInst); + case 0x11: return new Deprecated_ivle(machInst); + case 0x20: return new Deprecated_exit (machInst); + case 0x21: return new M5exit(machInst); +#if FULL_SYSTEM + case 0x31: return new Loadsymbol(machInst); + case 0x30: return new Initparam(machInst); +#endif + case 0x40: return new Resetstats(machInst); + case 0x41: return new Dumpstats(machInst); + case 0x42: return new Dumpresetstats(machInst); + case 0x43: return new M5checkpoint(machInst); +#if FULL_SYSTEM + case 0x50: return new M5readfile(machInst); +#endif + case 0x51: return new M5break(machInst); + case 0x52: return new M5switchcpu(machInst); +#if FULL_SYSTEM + case 0x53: return new M5addsymbol(machInst); +#endif + case 0x54: return new M5panic(machInst); + } + } + ''' +}}; |