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-rw-r--r--src/arch/arm/isa/formats/mem.isa30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 41706c48d..5d389458c 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -255,6 +255,36 @@ def format ArmSyncMem() {{
}
}};
+def format Thumb32SrsRfe() {{
+ decode_block = '''
+ {
+ if (bits(machInst, 20) == 1) {
+ const bool add = (bits(machInst, 24, 23) == 0x3);
+ // post == add
+ const bool wb = (bits(machInst, 21) == 1);
+ const IntRegIndex rn =
+ (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ if (!add && !wb) {
+ return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb);
+ } else if (add && !wb) {
+ return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb);
+ } else if (!add && wb) {
+ return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb);
+ } else {
+ return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb);
+ }
+ } else {
+ return new WarnUnimplemented("srs", machInst);
+ }
+ }
+ ''' % {
+ "rfe" : "RFE_" + loadImmClassName(False, False, False, 8),
+ "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
+ "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8),
+ "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8)
+ }
+}};
+
def format Thumb32LdrStrDExTbh() {{
decode_block = '''
{