diff options
Diffstat (limited to 'src/arch/arm/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index bc3c1f720..1602997dd 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -358,6 +358,46 @@ def format Thumb32StoreSingle() {{ decode_block = decode % classNames }}; +def format Thumb16MemReg() {{ + decode = ''' + { + const uint32_t opb = bits(machInst, 11, 9); + const uint32_t rt = bits(machInst, 2, 0); + const uint32_t rn = bits(machInst, 5, 3); + const uint32_t rm = bits(machInst, 8, 6); + switch (opb) { + case 0x0: + return new %(str)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x1: + return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x2: + return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x3: + return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x4: + return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x5: + return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x6: + return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm); + case 0x7: + return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm); + } + } + ''' + classNames = { + "str" : storeRegClassName(False, True, False), + "strh" : storeRegClassName(False, True, False, size=2), + "strb" : storeRegClassName(False, True, False, size=1), + "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1), + "ldr" : loadRegClassName(False, True, False), + "ldrh" : loadRegClassName(False, True, False, size=2), + "ldrb" : loadRegClassName(False, True, False, size=1), + "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), + } + decode_block = decode % classNames +}}; + def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }}, mem_flags = [], inst_flags = []) {{ ea_code = ArmGenericCodeSubs(ea_code) |