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-rw-r--r--src/arch/arm/isa/formats/misc.isa3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 4a9200504..54482864a 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
case MISCREG_L2LATENCY:
return new WarnUnimplemented(
isRead ? "mrc l2latency" : "mcr l2latency", machInst);
+ case MISCREG_CRN15:
+ return new WarnUnimplemented(
+ isRead ? "mrc crn15" : "mcr crn15", machInst);
// Write only.
case MISCREG_TLBIALLIS: