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Diffstat (limited to 'src/arch/arm/isa/formats/pred.isa')
-rw-r--r--src/arch/arm/isa/formats/pred.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 897edc2dc..18df8491c 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -150,10 +150,10 @@ def format DataOp(code, flagtype = logic) {{
"predicate_test": predicateTest})
regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
{"code": regCode + regCcCode,
- "predicate_test": predicateTest})
+ "predicate_test": condPredicateTest})
immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
{"code": immCode + immCcCode,
- "predicate_test": predicateTest})
+ "predicate_test": condPredicateTest})
header_output = BasicDeclare.subst(regIop) + \
BasicDeclare.subst(immIop) + \
BasicDeclare.subst(regCcIop) + \
@@ -176,7 +176,7 @@ def format DataImmOp(code, flagtype = logic) {{
"predicate_test": predicateTest})
ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
{"code": code + getImmCcCode(flagtype),
- "predicate_test": predicateTest})
+ "predicate_test": condPredicateTest})
header_output = BasicDeclare.subst(iop) + \
BasicDeclare.subst(ccIop)
decoder_output = BasicConstructor.subst(iop) + \