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-rw-r--r--src/arch/arm/isa/insts/div.isa6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index 302beb6b3..d736f9230 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -56,7 +56,8 @@ let {{
'''
sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
{ "code": sdivCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "IntDivOp"}, [])
header_output = RegRegRegOpDeclare.subst(sdivIop)
decoder_output = RegRegRegOpConstructor.subst(sdivIop)
exec_output = PredOpExecute.subst(sdivIop)
@@ -77,7 +78,8 @@ let {{
'''
udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
{ "code": udivCode,
- "predicate_test": predicateTest }, [])
+ "predicate_test": predicateTest,
+ "op_class": "IntDivOp"}, [])
header_output += RegRegRegOpDeclare.subst(udivIop)
decoder_output += RegRegRegOpConstructor.subst(udivIop)
exec_output += PredOpExecute.subst(udivIop)