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-rw-r--r--src/arch/arm/isa/insts/fp.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 961b9a355..4911d50f1 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -209,7 +209,8 @@ let {{
{ "code": vmsrFpscrCode,
"predicate_test": predicateTest,
"op_class": "SimdFloatMiscOp" },
- ["IsSerializeAfter","IsNonSpeculative"])
+ ["IsSerializeAfter","IsNonSpeculative",
+ "IsSquashAfter"])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop);