diff options
Diffstat (limited to 'src/arch/arm/isa/insts/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 35d0405e9..9969e6711 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -678,4 +678,29 @@ let {{ header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop); decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop); exec_output += PredOpExecute.subst(vcvtFpSIntDIop); + + vcvtFpSFpDCode = ''' + IntDoubleUnion cDest; + cDest.fp = FpOp1; + FpDestP0.uw = cDest.bits; + FpDestP1.uw = cDest.bits >> 32; + ''' + vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "RegRegOp", + { "code": vcvtFpSFpDCode, + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(vcvtFpSFpDIop); + decoder_output += RegRegOpConstructor.subst(vcvtFpSFpDIop); + exec_output += PredOpExecute.subst(vcvtFpSFpDIop); + + vcvtFpDFpSCode = ''' + IntDoubleUnion cOp1; + cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); + FpDest = cOp1.fp; + ''' + vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "RegRegOp", + { "code": vcvtFpDFpSCode, + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(vcvtFpDFpSIop); + decoder_output += RegRegOpConstructor.subst(vcvtFpDFpSIop); + exec_output += PredOpExecute.subst(vcvtFpDFpSIop); }}; |