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-rw-r--r--src/arch/arm/isa/insts/fp.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index dc2f30701..dff906755 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -224,7 +224,7 @@ let {{
if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
HCR hcr = Hcr;
bool hypTrap = false;
- switch(xc->tcBase()->flattenMiscIndex(op1)) {
+ switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) {
case MISCREG_FPSID:
hypTrap = hcr.tid0;
break;