diff options
Diffstat (limited to 'src/arch/arm/isa/insts/fp.isa')
-rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 233 |
1 files changed, 124 insertions, 109 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 68c294851..961b9a355 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -208,7 +208,8 @@ let {{ vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", { "code": vmsrFpscrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeAfter","IsNonSpeculative"]) header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); exec_output += PredOpExecute.subst(vmsrFpscrIop); @@ -217,7 +218,8 @@ let {{ { "code": vmrsEnabledCheckCode + \ "Dest = MiscOp1;", "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegOpDeclare.subst(vmrsIop); decoder_output += FpRegRegOpConstructor.subst(vmrsIop); exec_output += PredOpExecute.subst(vmrsIop); @@ -226,7 +228,8 @@ let {{ { "code": vmrsEnabledCheckCode + \ "Dest = Fpscr | FpCondCodes;", "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); @@ -237,7 +240,8 @@ let {{ vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", { "code": vmrsApsrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); exec_output += PredOpExecute.subst(vmrsApsrIop); @@ -249,7 +253,8 @@ let {{ vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", { "code": vmrsApsrFpscrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, []) + "op_class": "SimdFloatMiscOp" }, + ["IsSerializeBefore"]) header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); @@ -451,20 +456,22 @@ let {{ decoder_output = "" exec_output = "" - singleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + singleSimpleCode = vfpEnabledCheckCode + ''' + FPSCR fpscr = (FPSCR) FpscrExc; FpDest = %(op)s; - FpCondCodes = fpscr & FpCondCodesMask; + ''' + singleCode = singleSimpleCode + ''' + FpscrExc = fpscr; ''' singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" doubleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double dest = %(op)s; - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' doubleBinOp = ''' binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), @@ -545,7 +552,7 @@ let {{ global header_output, decoder_output, exec_output sIop = InstObjParams(name + "s", Name + "S", base, - { "code": singleCode % { "op": singleOp }, + { "code": singleSimpleCode % { "op": singleOp }, "predicate_test": predicateTest, "op_class": opClass }, []) dIop = InstObjParams(name + "d", Name + "D", base, @@ -574,12 +581,12 @@ let {{ exec_output = "" vmlaSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; float mid = binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", { "code": vmlaSCode, @@ -590,16 +597,16 @@ let {{ exec_output += PredOpExecute.subst(vmlaSIop); vmlaDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), dbl(FpOp2P0.uw, FpOp2P1.uw), fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), mid, fpAddD, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", { "code": vmlaDCode, @@ -610,12 +617,12 @@ let {{ exec_output += PredOpExecute.subst(vmlaDIop); vmlsSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; float mid = binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", { "code": vmlsSCode, @@ -626,16 +633,16 @@ let {{ exec_output += PredOpExecute.subst(vmlsSIop); vmlsDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), dbl(FpOp2P0.uw, FpOp2P1.uw), fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), -mid, fpAddD, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", { "code": vmlsDCode, @@ -646,12 +653,12 @@ let {{ exec_output += PredOpExecute.subst(vmlsDIop); vnmlaSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; float mid = binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", { "code": vnmlaSCode, @@ -662,16 +669,16 @@ let {{ exec_output += PredOpExecute.subst(vnmlaSIop); vnmlaDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), dbl(FpOp2P0.uw, FpOp2P1.uw), fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), -mid, fpAddD, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", { "code": vnmlaDCode, @@ -682,12 +689,12 @@ let {{ exec_output += PredOpExecute.subst(vnmlaDIop); vnmlsSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; float mid = binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", { "code": vnmlsSCode, @@ -698,16 +705,16 @@ let {{ exec_output += PredOpExecute.subst(vnmlsSIop); vnmlsDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), dbl(FpOp2P0.uw, FpOp2P1.uw), fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), mid, fpAddD, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", { "code": vnmlsDCode, @@ -718,10 +725,10 @@ let {{ exec_output += PredOpExecute.subst(vnmlsDIop); vnmulSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", { "code": vnmulSCode, @@ -732,14 +739,14 @@ let {{ exec_output += PredOpExecute.subst(vnmulSIop); vnmulDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), dbl(FpOp2P0.uw, FpOp2P1.uw), fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(dest); FpDestP1.uw = dblHi(dest); + FpscrExc = fpscr; ''' vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", { "code": vnmulDCode, @@ -757,13 +764,13 @@ let {{ exec_output = "" vcvtUIntFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); FpDest = FpOp1.uw; __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", { "code": vcvtUIntFpSCode, @@ -774,15 +781,15 @@ let {{ exec_output += PredOpExecute.subst(vcvtUIntFpSIop); vcvtUIntFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); double cDest = (uint64_t)FpOp1P0.uw; __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", { "code": vcvtUIntFpDCode, @@ -793,13 +800,13 @@ let {{ exec_output += PredOpExecute.subst(vcvtUIntFpDIop); vcvtSIntFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); FpDest = FpOp1.sw; __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", { "code": vcvtSIntFpSCode, @@ -810,15 +817,15 @@ let {{ exec_output += PredOpExecute.subst(vcvtSIntFpSIop); vcvtSIntFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); double cDest = FpOp1P0.sw; __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", { "code": vcvtSIntFpDCode, @@ -829,14 +836,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtSIntFpDIop); vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); vfpFlushToZero(fpscr, FpOp1); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); __asm__ __volatile__("" :: "m" (FpDest.uw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", { "code": vcvtFpUIntSRCode, @@ -847,7 +854,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -855,8 +862,8 @@ let {{ uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); __asm__ __volatile__("" :: "m" (result)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = result; + FpscrExc = fpscr; ''' vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", { "code": vcvtFpUIntDRCode, @@ -867,14 +874,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); vfpFlushToZero(fpscr, FpOp1); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); __asm__ __volatile__("" :: "m" (FpDest.sw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", { "code": vcvtFpSIntSRCode, @@ -885,7 +892,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -893,8 +900,8 @@ let {{ int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); __asm__ __volatile__("" :: "m" (result)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = result; + FpscrExc = fpscr; ''' vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", { "code": vcvtFpSIntDRCode, @@ -905,7 +912,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); vcvtFpUIntSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); fesetround(FeRoundZero); @@ -913,7 +920,7 @@ let {{ FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); __asm__ __volatile__("" :: "m" (FpDest.uw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", { "code": vcvtFpUIntSCode, @@ -924,7 +931,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUIntSIop); vcvtFpUIntDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -933,8 +940,8 @@ let {{ uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); __asm__ __volatile__("" :: "m" (result)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = result; + FpscrExc = fpscr; ''' vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", { "code": vcvtFpUIntDCode, @@ -945,7 +952,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUIntDIop); vcvtFpSIntSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); fesetround(FeRoundZero); @@ -953,7 +960,7 @@ let {{ FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); __asm__ __volatile__("" :: "m" (FpDest.sw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", { "code": vcvtFpSIntSCode, @@ -964,7 +971,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSIntSIop); vcvtFpSIntDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -973,8 +980,8 @@ let {{ int64_t result = vfpFpDToFixed(cOp1, true, false, 0); __asm__ __volatile__("" :: "m" (result)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = result; + FpscrExc = fpscr; ''' vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", { "code": vcvtFpSIntDCode, @@ -985,16 +992,16 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSIntDIop); vcvtFpSFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); - double cDest = fixFpSFpDDest(Fpscr, FpOp1); + double cDest = fixFpSFpDDest(FpscrExc, FpOp1); __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", { "code": vcvtFpSFpDCode, @@ -1005,15 +1012,15 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSFpDIop); vcvtFpDFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); - FpDest = fixFpDFpSDest(Fpscr, cOp1); + FpDest = fixFpDFpSDest(FpscrExc, cOp1); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", { "code": vcvtFpDFpSCode, @@ -1024,7 +1031,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpDFpSIop); vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); @@ -1032,7 +1039,7 @@ let {{ bits(fpToBits(FpOp1), 31, 16)); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", { "code": vcvtFpHTFpSCode, @@ -1043,14 +1050,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, bits(fpToBits(FpOp1), 15, 0)); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", { "code": vcvtFpHBFpSCode, @@ -1061,7 +1068,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) @@ -1071,7 +1078,7 @@ let {{ fpscr.rMode, fpscr.ahp, FpOp1)); __asm__ __volatile__("" :: "m" (FpDest.uw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", { "code": vcvtFpHTFpSCode, @@ -1082,7 +1089,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) @@ -1092,7 +1099,7 @@ let {{ fpscr.rMode, fpscr.ahp, FpOp1)); __asm__ __volatile__("" :: "m" (FpDest.uw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", { "code": vcvtFpSFpHBCode, @@ -1103,7 +1110,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); vcmpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpDest, FpOp1); if (FpDest == FpOp1) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1122,6 +1129,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", { "code": vcmpSCode, @@ -1134,7 +1142,7 @@ let {{ vcmpDCode = vfpEnabledCheckCode + ''' double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cDest = dbl(FpDestP0.uw, FpDestP1.uw); - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, cDest, cOp1); if (cDest == cOp1) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1153,6 +1161,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", { "code": vcmpDCode, @@ -1163,7 +1172,7 @@ let {{ exec_output += PredOpExecute.subst(vcmpDIop); vcmpZeroSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpDest); // This only handles imm == 0 for now. assert(imm == 0); @@ -1182,6 +1191,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", { "code": vcmpZeroSCode, @@ -1195,7 +1205,7 @@ let {{ // This only handles imm == 0 for now. assert(imm == 0); double cDest = dbl(FpDestP0.uw, FpDestP1.uw); - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, cDest); if (cDest == imm) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1212,6 +1222,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", { "code": vcmpZeroDCode, @@ -1222,7 +1233,7 @@ let {{ exec_output += PredOpExecute.subst(vcmpZeroDIop); vcmpeSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpDest, FpOp1); if (FpDest == FpOp1) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1235,6 +1246,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", { "code": vcmpeSCode, @@ -1247,7 +1259,7 @@ let {{ vcmpeDCode = vfpEnabledCheckCode + ''' double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cDest = dbl(FpDestP0.uw, FpDestP1.uw); - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, cDest, cOp1); if (cDest == cOp1) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1260,6 +1272,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", { "code": vcmpeDCode, @@ -1270,7 +1283,7 @@ let {{ exec_output += PredOpExecute.subst(vcmpeDIop); vcmpeZeroSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpDest); if (FpDest == imm) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1283,6 +1296,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", { "code": vcmpeZeroSCode, @@ -1294,7 +1308,7 @@ let {{ vcmpeZeroDCode = vfpEnabledCheckCode + ''' double cDest = dbl(FpDestP0.uw, FpDestP1.uw); - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, cDest); if (cDest == imm) { fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; @@ -1307,6 +1321,7 @@ let {{ fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; } FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", { "code": vcmpeZeroDCode, @@ -1324,14 +1339,14 @@ let {{ exec_output = "" vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); __asm__ __volatile__("" :: "m" (FpDest.sw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", { "code": vcvtFpSFixedSCode, @@ -1342,7 +1357,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -1350,9 +1365,9 @@ let {{ uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); __asm__ __volatile__("" :: "m" (mid)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = mid; FpDestP1.uw = mid >> 32; + FpscrExc = fpscr; ''' vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", { "code": vcvtFpSFixedDCode, @@ -1363,14 +1378,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); __asm__ __volatile__("" :: "m" (FpDest.uw)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", { "code": vcvtFpUFixedSCode, @@ -1381,7 +1396,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -1389,9 +1404,9 @@ let {{ uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); __asm__ __volatile__("" :: "m" (mid)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = mid; FpDestP1.uw = mid >> 32; + FpscrExc = fpscr; ''' vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", { "code": vcvtFpUFixedDCode, @@ -1402,13 +1417,13 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", { "code": vcvtSFixedFpSCode, @@ -1419,16 +1434,16 @@ let {{ exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", { "code": vcvtSFixedFpDCode, @@ -1439,13 +1454,13 @@ let {{ exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", { "code": vcvtUFixedFpSCode, @@ -1456,16 +1471,16 @@ let {{ exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", { "code": vcvtUFixedFpDCode, @@ -1476,14 +1491,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); __asm__ __volatile__("" :: "m" (FpDest.sh)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", "FpRegRegImmOp", @@ -1495,7 +1510,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -1503,9 +1518,9 @@ let {{ uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); __asm__ __volatile__("" :: "m" (result)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = result; FpDestP1.uw = result >> 32; + FpscrExc = fpscr; ''' vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", "FpRegRegImmOp", @@ -1517,14 +1532,14 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; vfpFlushToZero(fpscr, FpOp1); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); __asm__ __volatile__("" :: "m" (FpDest.uh)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", "FpRegRegImmOp", @@ -1536,7 +1551,7 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); vfpFlushToZero(fpscr, cOp1); VfpSavedState state = prepFpState(fpscr.rMode); @@ -1544,9 +1559,9 @@ let {{ uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); __asm__ __volatile__("" :: "m" (mid)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = mid; FpDestP1.uw = mid >> 32; + FpscrExc = fpscr; ''' vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", "FpRegRegImmOp", @@ -1558,13 +1573,13 @@ let {{ exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", "FpRegRegImmOp", @@ -1576,16 +1591,16 @@ let {{ exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", "FpRegRegImmOp", @@ -1597,13 +1612,13 @@ let {{ exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); __asm__ __volatile__("" :: "m" (FpDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; + FpscrExc = fpscr; ''' vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", "FpRegRegImmOp", @@ -1615,16 +1630,16 @@ let {{ exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = Fpscr | FpCondCodes; + FPSCR fpscr = (FPSCR) FpscrExc; uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); VfpSavedState state = prepFpState(fpscr.rMode); __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); __asm__ __volatile__("" :: "m" (cDest)); finishVfp(fpscr, state, fpscr.fz); - FpCondCodes = fpscr & FpCondCodesMask; FpDestP0.uw = dblLow(cDest); FpDestP1.uw = dblHi(cDest); + FpscrExc = fpscr; ''' vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", "FpRegRegImmOp", |