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-rw-r--r--src/arch/arm/isa/insts/ldr64.isa7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 56112a7c1..801316eeb 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -99,6 +99,13 @@ let {{
if self.flavor in ("acex", "exclusive", "exp", "acexp"):
self.memFlags.append("Request::LLSC")
+ # Using a different execute template for fp flavoured loads.
+ # In this specific template the memacc_code is executed
+ # conditionally depending of wether the memory load has
+ # generated any fault
+ if flavor == "fp":
+ self.fullExecTemplate = eval(self.execBase + 'FpExecute')
+
def buildEACode(self):
# Address computation code
eaCode = ""