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-rw-r--r--src/arch/arm/isa/insts/misc.isa8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 35df88c81..7333faef0 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -680,18 +680,14 @@ let {{
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
- unsigned memAccessFlags = Request::CLEAR_LL |
- ArmISA::TLB::AlignWord | Request::LLSC;
- fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
+ LLSCLock = 0;
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
{ "code": clrexCode,
"predicate_test": predicateTest },[])
- header_output += ClrexDeclare.subst(clrexIop)
+ header_output += BasicDeclare.subst(clrexIop)
decoder_output += BasicConstructor.subst(clrexIop)
exec_output += PredOpExecute.subst(clrexIop)
- exec_output += ClrexInitiateAcc.subst(clrexIop)
- exec_output += ClrexCompleteAcc.subst(clrexIop)
isbCode = '''
fault = new FlushPipe;