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-rw-r--r--src/arch/arm/isa/insts/misc.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 495cb722c..b671843cf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -49,7 +49,8 @@ let {{
svcIop = InstObjParams("svc", "Svc", "PredOp",
{ "code": svcCode,
- "predicate_test": predicateTest }, ["IsSyscall"])
+ "predicate_test": predicateTest },
+ ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
header_output = BasicDeclare.subst(svcIop)
decoder_output = BasicConstructor.subst(svcIop)
exec_output = PredOpExecute.subst(svcIop)