1 files changed, 20 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 2483b75b0..faac5cfcf 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013, 2016-2017 ARM Limited
+// Copyright (c) 2011-2013, 2016-2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -174,4 +174,23 @@ let {{
     header_output += BasicDeclare.subst(brkIop)
     decoder_output += BasicConstructor64.subst(brkIop)
     exec_output += BasicExecute.subst(brkIop)
+
+    hltCode = '''
+    ThreadContext *tc = xc->tcBase();
+    if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) {
+        X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
+    } else {
+        // HLT instructions aren't implemented, so treat them as undefined
+        // instructions.
+        fault = std::make_shared<UndefinedInstruction>(
+            machInst, false, mnemonic);
+    }
+
+    '''
+
+    hltIop = InstObjParams("hlt", "Hlt64", "ArmStaticInst",
+                           hltCode, ["IsNonSpeculative"])
+    header_output += BasicDeclare.subst(hltIop)
+    decoder_output += BasicConstructor64.subst(hltIop)
+    exec_output += BasicExecute.subst(hltIop)
 }};