1 files changed, 19 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 7e88bebbb..08902abe8 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013 ARM Limited
+// Copyright (c) 2011-2013, 2016 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -49,6 +49,24 @@ let {{
     decoder_output = BasicConstructor64.subst(svcIop)
     exec_output = BasicExecute.subst(svcIop)
 
+    hvcCode = '''
+    SCR scr = Scr64;
+
+    if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
+        (ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) {
+        fault = disabledFault();
+    } else {
+        fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5));
+    }
+    '''
+
+    hvcIop = InstObjParams("hvc", "Hvc64", "ArmStaticInst",
+                           hvcCode, ["IsSyscall", "IsNonSpeculative",
+                                     "IsSerializeAfter"])
+    header_output += BasicDeclare.subst(hvcIop)
+    decoder_output += BasicConstructor64.subst(hvcIop)
+    exec_output += BasicExecute.subst(hvcIop)
+
     # @todo: extend to take into account Virtualization.
     smcCode = '''
     SCR scr = Scr64;