summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/mult.isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa/insts/mult.isa')
-rw-r--r--src/arch/arm/isa/insts/mult.isa8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index ae8f04a81..b3a9fca5f 100644
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -349,8 +349,8 @@ let {{
''')
buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2.sw *
(int64_t)Reg3.sw;
- Reg0 = (int32_t)resTemp;
Reg1 = (int32_t)(resTemp >> 32);
+ Reg0 = (int32_t)resTemp;
''', "llbit")
buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
(Reg1.sw *
@@ -374,16 +374,16 @@ let {{
''')
buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
Reg0.ud + Reg1.ud;
- Reg0.ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32);
+ Reg0.ud = (uint32_t)resTemp;
''')
buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
(Reg1.ud << 32);
- Reg0.ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32);
+ Reg0.ud = (uint32_t)resTemp;
''', "llbit")
buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud;
- Reg0 = (uint32_t)resTemp;
Reg1 = (uint32_t)(resTemp >> 32);
+ Reg0 = (uint32_t)resTemp;
''', "llbit")
}};