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Diffstat (limited to 'src/arch/arm/isa/insts/neon.isa')
-rw-r--r--src/arch/arm/isa/insts/neon.isa15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 1b20c660d..163b71c13 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2939,29 +2939,32 @@ let {{
twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True)
vsriCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = destElem;
- else
+ } else {
destElem = (srcElem1 >> imm) |
(destElem & ~mask(sizeof(Element) * 8 - imm));
+ }
'''
twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True)
twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True)
vshlCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1;
- else
+ } else {
destElem = srcElem1 << imm;
+ }
'''
twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode)
twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode)
vsliCode = '''
- if (imm >= sizeof(Element) * 8)
+ if (imm >= sizeof(Element) * 8) {
destElem = destElem;
- else
+ } else {
destElem = (srcElem1 << imm) | (destElem & mask(imm));
+ }
'''
twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True)
twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True)