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-rw-r--r--src/arch/arm/isa/insts/neon64.isa3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index e065761f4..bbe57bdfa 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1959,6 +1959,9 @@ let {{
2, minAcrossCode)
twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4,
minAcrossCode)
+
+ split('exec')
+
# SMLAL, SMLAL2 (by element)
mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;"
threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp",