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Diffstat (limited to 'src/arch/arm/isa/insts/str.isa')
-rw-r--r--src/arch/arm/isa/insts/str.isa18
1 files changed, 14 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index c22245947..0c92b20df 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -93,7 +93,8 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
+ { "suffix" : buildMemSuffix(sign, size) }
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryImm", post, writeback)
@@ -121,7 +122,8 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \
+ { "suffix" : buildMemSuffix(sign, size) }
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryReg", post, writeback)
@@ -146,7 +148,11 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
+ accCode = '''
+ CPSR cpsr = Cpsr;
+ Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
+ ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
+ '''
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryDImm", post, writeback)
@@ -171,7 +177,11 @@ let {{
eaCode += offset
eaCode += ";"
- accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
+ accCode = '''
+ CPSR cpsr = Cpsr;
+ Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
+ ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
+ '''
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryDReg", post, writeback)