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-rw-r--r--src/arch/arm/isa/insts/str.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index e5d47c28f..312bcac16 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -152,7 +152,7 @@ let {{
def __init__(self, *args, **kargs):
super(StoreRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodes<29:>)"
+ " shiftType, CondCodesF<29:>)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);