summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/str64.isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa/insts/str64.isa')
-rw-r--r--src/arch/arm/isa/insts/str64.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index 0b153c1ec..324d1fc69 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -226,9 +226,9 @@ let {{
accCode = '''
// This temporary needs to be here so that the parser
// will correctly identify this instruction as a store.
- Twin64_t temp;
- temp.a = XDest_ud;
- temp.b = XDest2_ud;
+ std::array<uint64_t, 2> temp;
+ temp[0] = XDest_ud;
+ temp[1] = XDest2_ud;
Mem_tud = temp;
'''
self.codeBlobs["memacc_code"] = accCode