diff options
Diffstat (limited to 'src/arch/arm/isa/insts/str64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/str64.isa | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa index c15dca16e..0b153c1ec 100644 --- a/src/arch/arm/isa/insts/str64.isa +++ b/src/arch/arm/isa/insts/str64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013 ARM Limited +// Copyright (c) 2011-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -277,7 +277,8 @@ let {{ execBase = 'StoreEx64' def __init__(self, *args, **kargs): super(StoreEx64, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "XResult = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" def buildStores64(mnem, NameBase, size, flavor="normal"): StoreImm64(mnem, NameBase + "_IMM", size, flavor=flavor).emit() @@ -343,7 +344,8 @@ let {{ writeback = False def __init__(self, *args, **kargs): super(StoreImmDEx64, self).__init__(*args, **kargs) - self.codeBlobs["postacc_code"] = "XResult = !writeResult;" + self.codeBlobs["postacc_code"] = \ + "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" class StoreRegU64(StoreReg64): decConstBase = 'LoadStoreRegU64' |