diff options
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index 3be4278fa..f319e75aa 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -82,7 +82,7 @@ let {{ ''' SwapInst('swp', 'Swp', 'EA = Base;', - swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);', 'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignWord', @@ -90,8 +90,8 @@ let {{ ['IsStoreConditional']).emit() SwapInst('swpb', 'Swpb', 'EA = Base;', - swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', - 'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);', + 'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignByte', 'ArmISA::TLB::MustBeOne'], |