2 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 82e9d9842..2b42dfac8 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -47,10 +47,6 @@
 //
 
 let {{
-    predicateTest = 'testPredicate(CondCodes, condCode)'
-}};
-
-let {{
     microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
     microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                    'MicroMemOp',
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 722b05eac..ee6330f48 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -456,10 +456,18 @@ let {{
     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
     exec_output += PredOpExecute.subst(usada8Iop)
 
-    nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", [])
+    nopIop = InstObjParams("nop", "NopInst", "PredOp", \
+            { "code" : "", "predicate_test" : predicateTest })
     header_output += BasicDeclare.subst(nopIop)
     decoder_output += BasicConstructor.subst(nopIop)
-    exec_output += BasicExecute.subst(nopIop)
+    exec_output += PredOpExecute.subst(nopIop)
+
+    itIop = InstObjParams("it", "ItInst", "PredOp", \
+            { "code" : "Itstate = machInst.newItstate;",
+              "predicate_test" : predicateTest })
+    header_output += BasicDeclare.subst(itIop)
+    decoder_output += BasicConstructor.subst(itIop)
+    exec_output += PredOpExecute.subst(itIop)
 
     ubfxCode = '''
         Dest = bits(Op1, imm2, imm1);