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-rw-r--r--src/arch/arm/isa/insts/ldr.isa6
-rw-r--r--src/arch/arm/isa/insts/str.isa13
2 files changed, 16 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 40d9147df..093ff7a60 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -93,6 +93,9 @@ let {{
eaCode += ";"
memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
+ if user:
+ memFlags.append("ArmISA::TLB::UserMode")
+
if prefetch:
Name = "%s_%s" % (mnem.upper(), Name)
memFlags.append("Request::PREFETCH")
@@ -179,6 +182,9 @@ let {{
eaCode += ";"
memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"]
+ if user:
+ memFlags.append("ArmISA::TLB::UserMode")
+
if prefetch:
Name = "%s_%s" % (mnem.upper(), Name)
memFlags.append("Request::PREFETCH")
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index c8d2679fc..d86000947 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -107,6 +107,9 @@ let {{
accCode += "Base = Base %s;\n" % offset
memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
+ if user:
+ memFlags.append("ArmISA::TLB::UserMode")
+
if strex:
memFlags.append("Request::LLSC")
Name = "%s_%s" % (mnem.upper(), Name)
@@ -184,10 +187,14 @@ let {{
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryReg", post, writeback)
- emitStore(name, Name, False, eaCode, accCode, "",\
- ["ArmISA::TLB::MustBeOne", \
+ memFlags = ["ArmISA::TLB::MustBeOne", \
"ArmISA::TLB::AllowUnaligned", \
- "%d" % (size - 1)], [], base)
+ "%d" % (size - 1)]
+ if user:
+ memFlags.append("ArmISA::TLB::UserMode")
+
+ emitStore(name, Name, False, eaCode, accCode, "",\
+ memFlags, [], base)
def buildDoubleImmStore(mnem, post, add, writeback, \
strex=False, vstr=False):