diff options
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/data.isa | 22 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 15 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 15 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/mem.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 41 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/mult.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/str.isa | 2 |
8 files changed, 54 insertions, 51 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 5b1526e41..a6d4c7daa 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -44,11 +44,11 @@ let {{ exec_output = "" calcGECode = ''' - CondCodes = insertBits(CondCodes, 19, 16, resTemp); + CondCodesGE = insertBits(0, 19, 16, resTemp); ''' calcQCode = ''' - CondCodes = CondCodes | ((resTemp & 1) << 27); + CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); ''' calcCcCode = ''' @@ -58,16 +58,15 @@ let {{ _iv = %(ivValue)s & 1; _ic = %(icValue)s & 1; - CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | - (CondCodes & 0x0FFFFFFF); + CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", _in, _iz, _ic, _iv); ''' # Dict of code to set the carry flag. (imm, reg, reg-reg) - oldC = 'CondCodes<29:>' - oldV = 'CondCodes<28:>' + oldC = 'CondCodesF<29:>' + oldV = 'CondCodesF<28:>' carryCode = { "none": (oldC, oldC, oldC), "llbit": (oldC, oldC, oldC), @@ -102,8 +101,8 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" - regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" + regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ buildCc = True, buildNonCc = True, instFlags = []): @@ -240,9 +239,12 @@ let {{ code += ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, + Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; + CondCodesF = CondCodesMaskF & newCpsr; + CondCodesQ = CondCodesMaskQ & newCpsr; + CondCodesGE = CondCodesMaskGE & newCpsr; NextThumb = ((CPSR)newCpsr).t; NextJazelle = ((CPSR)newCpsr).j; NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 4911d50f1..53d0b3413 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -235,21 +235,8 @@ let {{ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrCode = vmrsEnabledCheckCode + ''' - Dest = (MiscOp1 & imm) | (Dest & ~imm); - ''' - vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", - { "code": vmrsApsrCode, - "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) - header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); - decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); - exec_output += PredOpExecute.subst(vmrsApsrIop); - vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' - assert((imm & ~FpCondCodesMask) == 0); - Dest = (FpCondCodes & imm) | (Dest & ~imm); + Dest = FpCondCodes & FpCondCodesMask; ''' vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", { "code": vmrsApsrFpscrCode, diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index bfa94103f..bf8034a9e 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -106,7 +106,7 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodes; + URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE; URa = cSwap<uint32_t>(Mem.ud, cpsr.e); URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); ''' @@ -137,7 +137,7 @@ let {{ def __init__(self, *args, **kargs): super(LoadRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodes<29:>)" + " shiftType, CondCodesF<29:>)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 67d8da572..5007c85e5 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -90,9 +90,12 @@ let {{ CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); + cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE, + Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; + CondCodesF = CondCodesMaskF & newCpsr; + CondCodesQ = CondCodesMaskQ & newCpsr; + CondCodesGE = CondCodesMaskGE & newCpsr; IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) | (((CPSR)Spsr).it1 & 0x3); @@ -585,7 +588,7 @@ let {{ {'code': '''URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, - CondCodes<29:>); + CondCodesF<29:>); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -601,7 +604,7 @@ let {{ {'code': '''URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, - CondCodes<29:>); + CondCodesF<29:>); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -631,7 +634,9 @@ let {{ NextJazelle = ((CPSR)newCpsr).j; NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); - CondCodes = CondCodesMask & newCpsr; + CondCodesF = CondCodesMaskF & newCpsr; + CondCodesQ = CondCodesMaskQ & newCpsr; + CondCodesGE = CondCodesMaskGE & newCpsr; ''' microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index ca0d701d3..0ebd34ad4 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -120,7 +120,7 @@ let {{ def pickPredicate(blobs): for val in blobs.values(): - if re.search('(?<!Opt)CondCodes', val): + if re.search('(?<!Opt)CondCodesF', val): return condPredicateTest return predicateTest diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index a9a375213..a08477703 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -60,7 +60,10 @@ let {{ header_output = decoder_output = exec_output = "" - mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" + mrsCpsrCode = ''' + Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF + ''' + mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", { "code": mrsCpsrCode, "predicate_test": condPredicateTest }, @@ -81,9 +84,12 @@ let {{ msrCpsrRegCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1, + byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; + CondCodesF = CondCodesMaskF & newCpsr; + CondCodesQ = CondCodesMaskQ & newCpsr; + CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", { "code": msrCpsrRegCode, @@ -105,9 +111,12 @@ let {{ msrCpsrImmCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm, + byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - CondCodes = CondCodesMask & newCpsr; + CondCodesF = CondCodesMaskF & newCpsr; + CondCodesQ = CondCodesMaskQ & newCpsr; + CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", { "code": msrCpsrImmCode, @@ -196,9 +205,9 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (satInt(res, operand, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); else - CondCodes = CondCodes; + CondCodesQ = CondCodesQ; Dest = res; ''' ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", @@ -212,9 +221,9 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (uSatInt(res, operand, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); else - CondCodes = CondCodes; + CondCodesQ = CondCodesQ; Dest = res; ''' usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", @@ -227,14 +236,14 @@ let {{ ssat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodes = CondCodes; + CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (satInt(res, argLow, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); replaceBits(resTemp, 15, 0, res); if (satInt(res, argHigh, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' @@ -248,14 +257,14 @@ let {{ usat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodes = CondCodes; + CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (uSatInt(res, argLow, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); replaceBits(resTemp, 15, 0, res); if (uSatInt(res, argHigh, imm)) - CondCodes = CondCodes | (1 << 27); + CondCodesQ = CondCodesQ | (1 << 27); replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' @@ -414,7 +423,7 @@ let {{ int low = i * 8; int high = low + 7; replaceBits(resTemp, high, low, - bits(CondCodes, 16 + i) ? + bits(CondCodesGE, 16 + i) ? bits(Op1, high, low) : bits(Op2, high, low)); } Dest = resTemp; diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index b3a9fca5f..b02386c63 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -44,7 +44,7 @@ let {{ exec_output = "" calcQCode = ''' - CondCodes = CondCodes | ((resTemp & 1) << 27); + CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); ''' calcCcCode = ''' @@ -52,7 +52,7 @@ let {{ _in = (resTemp >> %(negBit)d) & 1; _iz = ((%(zType)s)resTemp == 0); - CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF); + CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); ''' diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index e5d47c28f..312bcac16 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -152,7 +152,7 @@ let {{ def __init__(self, *args, **kargs): super(StoreRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodes<29:>)" + " shiftType, CondCodesF<29:>)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); |