diff options
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 7f9a5c171..6b81853f1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -614,6 +614,20 @@ let {{ decoder_output += RegRegOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) + mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc15UserIop) + decoder_output += RegRegOpConstructor.subst(mrc15UserIop) + exec_output += PredOpExecute.subst(mrc15UserIop) + + mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", + { "code": "MiscDest = Op1", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mcr15UserIop) + decoder_output += RegRegOpConstructor.subst(mcr15UserIop) + exec_output += PredOpExecute.subst(mcr15UserIop) + enterxCode = ''' FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift); ''' |