summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/misc.isa9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 33197eaec..120372603 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -708,6 +708,15 @@ let {{
decoder_output += BasicConstructor.subst(dmbIop)
exec_output += PredOpExecute.subst(dmbIop)
+ dbgCode = '''
+ '''
+ dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
+ {"code": dbgCode,
+ "predicate_test": predicateTest})
+ header_output += BasicDeclare.subst(dbgIop)
+ decoder_output += BasicConstructor.subst(dbgIop)
+ exec_output += PredOpExecute.subst(dbgIop)
+
cpsCode = '''
uint32_t mode = bits(imm, 4, 0);
uint32_t f = bits(imm, 5);