diff options
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/branch.isa | 56 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/data.isa | 7 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 24 |
5 files changed, 70 insertions, 27 deletions
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa index e9ddd77b7..3ff9042e6 100644 --- a/src/arch/arm/isa/insts/branch.isa +++ b/src/arch/arm/isa/insts/branch.isa @@ -46,15 +46,17 @@ let {{ # B, BL for (mnem, link) in (("b", False), ("bl", True)): bCode = ''' - Addr curPc = readPC(xc); - NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32)); + ArmISA::PCState pc = PCS; + Addr curPc = pc.instPC(); + pc.instNPC((uint32_t)(curPc + imm)); + PCS = pc; ''' if (link): bCode += ''' - if (!isThumb(curPc)) - LR = curPc - 4; - else + if (pc.thumb()) LR = curPc | 1; + else + LR = curPc - 4; ''' bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", @@ -66,10 +68,12 @@ let {{ # BX, BLX blxCode = ''' - Addr curPc M5_VAR_USED = readPC(xc); + ArmISA::PCState pc = PCS; + Addr curPc M5_VAR_USED = pc.instPC(); %(link)s // Switch modes %(branch)s + PCS = pc; ''' blxList = (("blx", True, True), @@ -81,8 +85,8 @@ let {{ if imm: Name += "Imm" # Since we're switching ISAs, the target ISA will be the opposite - # of the current ISA. !arm is whether the target is ARM. - newPC = '(isThumb(curPc) ? (roundDown(curPc, 4) + imm) : (curPc + imm))' + # of the current ISA. pc.thumb() is whether the target is ARM. + newPC = '(pc.thumb() ? (roundDown(curPc, 4) + imm) : (curPc + imm))' base = "BranchImmCond" declare = BranchImmCondDeclare constructor = BranchImmCondConstructor @@ -97,28 +101,28 @@ let {{ // The immediate version of the blx thumb instruction // is 32 bits wide, but "next pc" doesn't reflect that // so we don't want to substract 2 from it at this point - if (!isThumb(curPc)) - LR = curPc - 4; - else + if (pc.thumb()) LR = curPc | 1; + else + LR = curPc - 4; ''' elif link: linkStr = ''' - if (!isThumb(curPc)) - LR = curPc - 4; - else + if (pc.thumb()) LR = (curPc - 2) | 1; + else + LR = curPc - 4; ''' else: linkStr = "" if imm and link: #blx with imm branchStr = ''' - Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32)); - FNPC = tempPc ^ PcTBit; + pc.nextThumb(!pc.thumb()); + pc.instNPC(%(newPC)s); ''' else: - branchStr = "IWNPC = %(newPC)s;" + branchStr = "pc.instIWNPC(%(newPC)s);" branchStr = branchStr % { "newPC" : newPC } code = blxCode % {"link": linkStr, @@ -136,8 +140,10 @@ let {{ #CBNZ, CBZ. These are always unconditional as far as predicates for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): code = ''' - Addr curPc = readPC(xc); - NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32)); + ArmISA::PCState pc = PCS; + Addr curPc = pc.instPC(); + pc.instNPC((uint32_t)(curPc + imm)); + PCS = pc; ''' predTest = "Op1 %(test)s 0" % {"test": test} iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", @@ -155,7 +161,11 @@ let {{ ArmISA::TLB::MustBeOne; EA = Op1 + Op2 * 2 ''' - accCode = "NPC = readPC(xc) + 2 * (Mem.uh);" + accCode = ''' + ArmISA::PCState pc = PCS; + pc.instNPC(pc.instPC() + 2 * (Mem.uh)); + PCS = pc; + ''' mnem = "tbh" else: eaCode = ''' @@ -164,7 +174,11 @@ let {{ ArmISA::TLB::MustBeOne; EA = Op1 + Op2 ''' - accCode = "NPC = readPC(xc) + 2 * (Mem.ub);" + accCode = ''' + ArmISA::PCState pc = PCS; + pc.instNPC(pc.instPC() + 2 * (Mem.ub)); + PCS = pc; + ''' mnem = "tbb" iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg", {'ea_code': eaCode, diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 74eeee3b2..4d368e181 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -239,6 +239,10 @@ let {{ cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodes = CondCodesMask & newCpsr; + ArmISA::PCState pc = PCS; + pc.nextThumb(((CPSR)newCpsr).t); + pc.nextJazelle(((CPSR)newCpsr).j); + PCS = pc; ''' buildImmDataInst(mnem + 's', code, flagType, suffix = "ImmPclr", buildCc = False, @@ -253,7 +257,8 @@ let {{ buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") buildImmDataInst("adr", ''' - Dest = resTemp = (readPC(xc) & ~0x3) + + ArmISA::PCState pc = PCS; + Dest = resTemp = (pc.instPC() & ~0x3) + (op1 ? secondOp : -secondOp); ''') buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index dc043ed8e..92ad52a6d 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -105,12 +105,16 @@ let {{ accCode = ''' CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; - NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); + ArmISA::PCState pc = PCS; + pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e)); uint32_t newCpsr = cpsrWriteByInstr(cpsr | CondCodes, cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; + pc.nextThumb(((CPSR)newCpsr).t); + pc.nextJazelle(((CPSR)newCpsr).j); + PCS = pc; CondCodes = CondCodesMask & newCpsr; ''' self.codeBlobs["memacc_code"] = accCode diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 6bf789efd..a81050b1e 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -93,7 +93,9 @@ let {{ cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodes = CondCodesMask & newCpsr; - IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); + ArmISA::PCState pc = PCS; + pc.instIWNPC(cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0)); + PCS = pc; ''' microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 'MicroMemOp', diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 5742f84ab..1abbc3de1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -83,6 +83,10 @@ let {{ uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; + ArmISA::PCState pc = PCS; + pc.nextThumb(((CPSR)newCpsr).t); + pc.nextJazelle(((CPSR)newCpsr).j); + PCS = pc; CondCodes = CondCodesMask & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -107,6 +111,10 @@ let {{ uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; + ArmISA::PCState pc = PCS; + pc.nextThumb(((CPSR)newCpsr).t); + pc.nextJazelle(((CPSR)newCpsr).j); + PCS = pc; CondCodes = CondCodesMask & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -462,8 +470,12 @@ let {{ decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) exec_output += PredOpExecute.subst(usada8Iop) + bkptCode = ''' + ArmISA::PCState pc = PCS; + return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent); + ''' bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst", - "return new PrefetchAbort(PC, ArmFault::DebugEvent);") + bkptCode) header_output += BasicDeclare.subst(bkptIop) decoder_output += BasicConstructor.subst(bkptIop) exec_output += BasicExecute.subst(bkptIop) @@ -638,7 +650,10 @@ let {{ exec_output += PredOpExecute.subst(mcr15UserIop) enterxCode = ''' - FNPC = NPC | PcJBit | PcTBit; + ArmISA::PCState pc = PCS; + pc.nextThumb(true); + pc.nextJazelle(true); + PCS = pc; ''' enterxIop = InstObjParams("enterx", "Enterx", "PredOp", { "code": enterxCode, @@ -648,7 +663,10 @@ let {{ exec_output += PredOpExecute.subst(enterxIop) leavexCode = ''' - FNPC = (NPC & ~PcJBit) | PcTBit; + ArmISA::PCState pc = PCS; + pc.nextThumb(true); + pc.nextJazelle(false); + PCS = pc; ''' leavexIop = InstObjParams("leavex", "Leavex", "PredOp", { "code": leavexCode, |