4 files changed, 12 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 474bd8c4e..09019d0f4 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -233,8 +233,9 @@ let {{
         buildRegRegDataInst(mnem, regRegCode, flagType)
         if subsPcLr:
             code += '''
+            SCTLR sctlr = Sctlr;
             uint32_t newCpsr =
-                cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
+                cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
             Cpsr = ~CondCodesMask & newCpsr;
             CondCodes = CondCodesMask & newCpsr;
             '''
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index f5ea53b72..40d9147df 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -137,11 +137,12 @@ let {{
             wbDiff = 8
         accCode = '''
         CPSR cpsr = Cpsr;
+        SCTLR sctlr = Sctlr;
         NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
         uint32_t newCpsr =
             cpsrWriteByInstr(cpsr | CondCodes,
                              cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
-                             0xF, true);
+                             0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
         '''
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 0870a966f..82e9d9842 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -69,8 +69,9 @@ let {{
 
     microLdrRetUopCode = '''
         CPSR cpsr = Cpsr;
+        SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
-            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true);
+            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
         IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 6cd4437d0..722b05eac 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -77,8 +77,9 @@ let {{
     exec_output += PredOpExecute.subst(mrsSpsrIop)
 
     msrCpsrRegCode = '''
+        SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
-            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
+            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
     '''
@@ -98,8 +99,9 @@ let {{
     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 
     msrCpsrImmCode = '''
+        SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
-            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
+            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
     '''
@@ -577,13 +579,14 @@ let {{
     bool setMode = bits(imm, 8);
     bool enable = bits(imm, 9);
     CPSR cpsr = Cpsr;
+    SCTLR sctlr = Sctlr;
     if (cpsr.mode != MODE_USER) {
         if (enable) {
             if (f) cpsr.f = 0;
             if (i) cpsr.i = 0;
             if (a) cpsr.a = 0;
         } else {
-            if (f) cpsr.f = 1;
+            if (f && !sctlr.nmfi) cpsr.f = 1;
             if (i) cpsr.i = 1;
             if (a) cpsr.a = 1;
         }