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-rw-r--r--src/arch/arm/isa/insts/data.isa5
-rw-r--r--src/arch/arm/isa/insts/ldr.isa2
-rw-r--r--src/arch/arm/isa/insts/macromem.isa4
-rw-r--r--src/arch/arm/isa/insts/misc.isa26
-rw-r--r--src/arch/arm/isa/insts/mult.isa2
5 files changed, 14 insertions, 25 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index a6d4c7daa..1a239f48b 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -48,7 +48,7 @@ let {{
'''
calcQCode = '''
- CondCodesQ = CondCodesQ | ((resTemp & 1) << 27);
+ CpsrQ = (resTemp & 1) << 27;
'''
calcCcCode = '''
@@ -239,11 +239,10 @@ let {{
code += '''
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE,
+ cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE,
Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesQ = CondCodesMaskQ & newCpsr;
CondCodesGE = CondCodesMaskGE & newCpsr;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index bf8034a9e..9211983d4 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -106,7 +106,7 @@ let {{
wbDiff = 8
accCode = '''
CPSR cpsr = Cpsr;
- URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE;
+ URc = cpsr | CondCodesF | CondCodesGE;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
'''
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 5007c85e5..8523b840c 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -90,11 +90,10 @@ let {{
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE,
+ cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE,
Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesQ = CondCodesMaskQ & newCpsr;
CondCodesGE = CondCodesMaskGE & newCpsr;
IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
@@ -635,7 +634,6 @@ let {{
NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesQ = CondCodesMaskQ & newCpsr;
CondCodesGE = CondCodesMaskGE & newCpsr;
'''
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index a08477703..c22384212 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -61,7 +61,7 @@ let {{
header_output = decoder_output = exec_output = ""
mrsCpsrCode = '''
- Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF
+ Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF
'''
mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
@@ -84,11 +84,10 @@ let {{
msrCpsrRegCode = '''
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1,
+ cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1,
byteMask, false, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesQ = CondCodesMaskQ & newCpsr;
CondCodesGE = CondCodesMaskGE & newCpsr;
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,11 +110,10 @@ let {{
msrCpsrImmCode = '''
SCTLR sctlr = Sctlr;
uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm,
+ cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm,
byteMask, false, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesQ = CondCodesMaskQ & newCpsr;
CondCodesGE = CondCodesMaskGE & newCpsr;
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -205,9 +203,7 @@ let {{
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;
if (satInt(res, operand, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
- else
- CondCodesQ = CondCodesQ;
+ CpsrQ = 1 << 27;
Dest = res;
'''
ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
@@ -221,9 +217,7 @@ let {{
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;
if (uSatInt(res, operand, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
- else
- CondCodesQ = CondCodesQ;
+ CpsrQ = 1 << 27;
Dest = res;
'''
usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
@@ -236,14 +230,13 @@ let {{
ssat16Code = '''
int32_t res;
uint32_t resTemp = 0;
- CondCodesQ = CondCodesQ;
int32_t argLow = sext<16>(bits(Op1, 15, 0));
int32_t argHigh = sext<16>(bits(Op1, 31, 16));
if (satInt(res, argLow, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
+ CpsrQ = 1 << 27;
replaceBits(resTemp, 15, 0, res);
if (satInt(res, argHigh, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
+ CpsrQ = 1 << 27;
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
@@ -257,14 +250,13 @@ let {{
usat16Code = '''
int32_t res;
uint32_t resTemp = 0;
- CondCodesQ = CondCodesQ;
int32_t argLow = sext<16>(bits(Op1, 15, 0));
int32_t argHigh = sext<16>(bits(Op1, 31, 16));
if (uSatInt(res, argLow, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
+ CpsrQ = 1 << 27;
replaceBits(resTemp, 15, 0, res);
if (uSatInt(res, argHigh, imm))
- CondCodesQ = CondCodesQ | (1 << 27);
+ CpsrQ = 1 << 27;
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index b02386c63..31febe747 100644
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -44,7 +44,7 @@ let {{
exec_output = ""
calcQCode = '''
- CondCodesQ = CondCodesQ | ((resTemp & 1) << 27);
+ CpsrQ = (resTemp & 1) << 27;
'''
calcCcCode = '''
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 08:43:10 +0000