diff options
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 30 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/str.isa | 24 |
2 files changed, 46 insertions, 8 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 3edeb3805..6e5122c6a 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011 ARM Limited +// Copyright (c) 2010-2011,2019 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -173,11 +173,17 @@ let {{ elif self.flavor == "iprefetch": self.memFlags.append("Request::PREFETCH") self.instFlags = ['IsInstPrefetch'] - elif self.flavor == "exclusive": - self.memFlags.append("Request::LLSC") elif self.flavor == "normal": self.memFlags.append("ArmISA::TLB::AllowUnaligned") + if self.flavor in ("exclusive", "acex"): + self.memFlags.append("Request::LLSC") + + if self.flavor in ("acquire", "acex"): + self.instFlags.extend(["IsMemBarrier", + "IsWriteBarrier", + "IsReadBarrier"]) + # Disambiguate the class name for different flavors of loads if self.flavor != "normal": self.Name = "%s_%s" % (self.name.upper(), self.Name) @@ -235,8 +241,9 @@ let {{ # Build the default class name self.Name = self.nameFunc(self.post, self.add, self.writeback) + self.instFlags = [] # Add memory request flags where necessary - if self.flavor == "exclusive": + if self.flavor in ("exclusive", "acex"): self.memFlags.append("Request::LLSC") self.memFlags.append("ArmISA::TLB::AlignDoubleWord") else: @@ -246,6 +253,11 @@ let {{ if self.flavor != "normal": self.Name = "%s_%s" % (self.name.upper(), self.Name) + if self.flavor in ("acquire", "acex"): + self.instFlags.extend(["IsMemBarrier", + "IsWriteBarrier", + "IsReadBarrier"]) + def emit(self): # Address computation code eaCode = "EA = Base" @@ -279,7 +291,7 @@ let {{ wbDecl = None if self.writeback: wbDecl = self.wbDecl - self.emitHelper(base, wbDecl) + self.emitHelper(base, wbDecl, self.instFlags) def loadDoubleImmClassName(post, add, writeback): return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) @@ -365,6 +377,14 @@ let {{ LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() + LoadImm("lda", False, True, False, size=4, flavor="acquire").emit() + LoadImm("ldah", False, True, False, size=2, flavor="acquire").emit() + LoadImm("ldab", False, True, False, size=1, flavor="acquire").emit() + LoadImm("ldaex", False, True, False, size=4, flavor="acex").emit() + LoadImm("ldaexh", False, True, False, size=2, flavor="acex").emit() + LoadImm("ldaexb", False, True, False, size=1, flavor="acex").emit() + LoadDoubleImm("ldaexd", False, True, False, flavor="acex").emit() + LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index ea412aa8d..6b2e8cc77 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011,2017 ARM Limited +// Copyright (c) 2010-2011,2017,2019 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -183,12 +183,17 @@ let {{ if self.user: self.memFlags.append("ArmISA::TLB::UserMode") - if self.flavor == "exclusive": + if self.flavor in ("exclusive", "relex"): self.instFlags.append("IsStoreConditional") self.memFlags.append("Request::LLSC") elif self.flavor != "fp": self.memFlags.append("ArmISA::TLB::AllowUnaligned") + if self.flavor in ("release", "relex"): + self.instFlags.extend(["IsMemBarrier", + "IsWriteBarrier", + "IsReadBarrier"]) + # Disambiguate the class name for different flavors of stores if self.flavor != "normal": self.Name = "%s_%s" % (self.name.upper(), self.Name) @@ -258,13 +263,18 @@ let {{ self.Name = self.nameFunc(self.post, self.add, self.writeback) # Add memory request flags where necessary - if self.flavor == "exclusive": + if self.flavor in ("exclusive", "relex"): self.instFlags.append("IsStoreConditional") self.memFlags.append("Request::LLSC") self.memFlags.append("ArmISA::TLB::AlignDoubleWord") else: self.memFlags.append("ArmISA::TLB::AlignWord") + if self.flavor in ("release", "relex"): + self.instFlags.extend(["IsMemBarrier", + "IsWriteBarrier", + "IsReadBarrier"]) + # Disambiguate the class name for different flavors of stores if self.flavor != "normal": self.Name = "%s_%s" % (self.name.upper(), self.Name) @@ -389,6 +399,14 @@ let {{ StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit() + StoreImm("stl", False, True, False, size=4, flavor="release").emit() + StoreImm("stlh", False, True, False, size=2, flavor="release").emit() + StoreImm("stlb", False, True, False, size=1, flavor="release").emit() + StoreImmEx("stlex", False, True, False, size=4, flavor="relex").emit() + StoreImmEx("stlexh", False, True, False, size=2, flavor="relex").emit() + StoreImmEx("stlexb", False, True, False, size=1, flavor="relex").emit() + StoreDoubleImmEx("stlexd", False, True, False, flavor="relex").emit() + StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() StoreDoubleImm("vstr", False, True, False, flavor="fp").emit() |