diff options
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/div.isa | 18 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/m5ops.isa | 5 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 51 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 41 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 9 |
5 files changed, 52 insertions, 72 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index 8a94d1ebd..1ff6ef9e4 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -41,11 +41,10 @@ let {{ sdivCode = ''' if (Op2_sw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_sw = 0; } else if (Op1_sw == INT_MIN && Op2_sw == -1) { @@ -65,11 +64,10 @@ let {{ udivCode = ''' if (Op2_uw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_uw = 0; } else { diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 3b837cba9..a157b414c 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -190,12 +190,7 @@ let {{ exec_output += PredOpExecute.subst(loadsymbolIop) initparamCode = ''' -#if FULL_SYSTEM Rt = PseudoInst::initParam(xc->tcBase()); -#else - PseudoInst::panicFsOnlyPseudoInst("initparam"); - Rt = 0; -#endif ''' initparamIop = InstObjParams("initparam", "Initparam", "PredOp", diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 870f037d0..b671843cf 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,11 +40,11 @@ let {{ svcCode = ''' -#if FULL_SYSTEM - fault = new SupervisorCall; -#else - fault = new SupervisorCall(machInst); -#endif + if (FullSystem) { + fault = new SupervisorCall; + } else { + fault = new SupervisorCall(machInst); + } ''' svcIop = InstObjParams("svc", "Svc", "PredOp", @@ -502,7 +502,6 @@ let {{ exec_output += PredOpExecute.subst(yieldIop) wfeCode = ''' -#if FULL_SYSTEM // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending if (SevMailbox == 1) { SevMailbox = 0; @@ -512,14 +511,11 @@ let {{ } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfePredFixUpCode = ''' -#if FULL_SYSTEM // WFE is predicated false, reset SevMailbox to reduce spurious sleeps // and SEV interrupts SevMailbox = 1; -#endif ''' wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ { "code" : wfeCode, @@ -531,14 +527,12 @@ let {{ exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) wfiCode = ''' -#if FULL_SYSTEM // WFI doesn't sleep if interrupts are pending (masked or not) if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { PseudoInst::quiesceSkip(xc->tcBase()); } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, @@ -548,7 +542,6 @@ let {{ exec_output += QuiescePredOpExecute.subst(wfiIop) sevCode = ''' -#if FULL_SYSTEM SevMailbox = 1; System *sys = xc->tcBase()->getSystemPtr(); for (int x = 0; x < sys->numContexts(); x++) { @@ -561,7 +554,6 @@ let {{ oc->getCpuPtr()->postInterrupt(INT_SEV, 0); } } -#endif ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, @@ -578,11 +570,10 @@ let {{ decoder_output += BasicConstructor.subst(itIop) exec_output += PredOpExecute.subst(itIop) unknownCode = ''' -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(machInst, true); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(machInst, true); ''' unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ { "code": unknownCode, @@ -635,12 +626,12 @@ let {{ mrc15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } Dest = MiscOp1; ''' @@ -654,12 +645,12 @@ let {{ mcr15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } MiscDest = Op1; ''' mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index dd0d49a5c..b1ad1eeb3 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -872,11 +872,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -927,11 +926,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -980,11 +978,10 @@ let {{ readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < rCount; i++) { FloatReg srcReg1 = srcRegs1[i]; @@ -3296,14 +3293,14 @@ let {{ destReg.elements[i] = srcReg1.elements[index]; } else { index -= eCount; - if (index >= eCount) -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif - else + if (index >= eCount) { + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); + } else { destReg.elements[i] = srcReg2.elements[index]; + } } } ''' diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index f319e75aa..b42a1c4b2 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -73,11 +73,10 @@ let {{ swpPreAccCode = ''' if (!((SCTLR)Sctlr).sw) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } ''' |