diff options
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 204 |
1 files changed, 98 insertions, 106 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 4f1b7f610..8e856e74d 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -54,11 +54,10 @@ def operand_types {{ let {{ maybePCRead = ''' - ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : - xc->%(func)s(this, %(op_idx)s)) + ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s)) ''' maybeAlignedPCRead = ''' - ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) : + ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) : xc->%(func)s(this, %(op_idx)s)) ''' maybePCWrite = ''' @@ -81,140 +80,133 @@ let {{ xc->%(func)s(this, %(op_idx)s, %(final_val)s); } ''' - - readNPC = 'xc->readNextPC() & ~PcModeMask' - writeNPC = 'setNextPC(xc, %(final_val)s)' - writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' - forceNPC = 'xc->setNextPC(%(final_val)s)' }}; def operands {{ #Abstracted integer reg operands - 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, + 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), - 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), - 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2), - 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2), - 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2), - 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2), - 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2), - 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2), - 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2), - 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2), - 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2), - 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2), - 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2), - 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2), - 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2), - 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2), - 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2), - 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, + 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3), + 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3), + 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3), + 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3), + 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3), + 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3), + 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3), + 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3), + 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3), + 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3), + 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3), + 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3), + 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3), + 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3), + 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3), + 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3), + 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3), + 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, + 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), - 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), - 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2), - 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2), - 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2), - 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, + 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3), + 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3), + 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3), + 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3), + 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3), + 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, maybePCRead, maybeIWPCWrite), - 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, + 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3, maybePCRead, maybeAIWPCWrite), 'SpMode': ('IntReg', 'uw', 'intRegInMode((OperatingMode)regMode, INTREG_SP)', - 'IsInteger', 2), - 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2), - 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0, + 'IsInteger', 3), + 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3), + 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, maybeAlignedPCRead, maybePCWrite), - 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, + 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, + 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), - 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), - 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2), - 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2), - 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2), - 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2), - 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2), - 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2), - 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2), - 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2), - 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2), - 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2), - 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2), - 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2), - 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2), - 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2), - 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2), - 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), - 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, + 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3), + 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3), + 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3), + 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3), + 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3), + 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3), + 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3), + 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3), + 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3), + 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3), + 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3), + 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3), + 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3), + 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3), + 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3), + 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3), + 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3), + 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3), + 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), - 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), - 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2), - 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2), - 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2), - 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2, + 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3), + 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3), + 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3), + 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3), + 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3), + 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2, + 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2, + 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2, + 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2, + 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3, maybePCRead, maybePCWrite), - 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2, + 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3, maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands - 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2), - 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2), + 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), + 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), - 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), - 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), + 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), + 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), 'OptCondCodes': ('IntReg', 'uw', '''(condCode == COND_AL || condCode == COND_UC) ? - INTREG_ZERO : INTREG_CONDCODES''', None, 2), - 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 2), + INTREG_ZERO : INTREG_CONDCODES''', None, 3), + 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3), #Register fields for microops - 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, + 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybeIWPCWrite), - 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), - 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), - 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3), + 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands - 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), - 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), - 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), + 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3), + 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3), + 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3), #Memory Operand - 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), + 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), - 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), - 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2), - 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), - 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), - 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), - 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2), - 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 2), - 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), - 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), - 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), - 'PC': ('PC', 'ud', None, None, 2), - 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, - readNPC, writeNPC), - 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, - readNPC, forceNPC), - 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, - readNPC, writeIWNPC), + 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), + 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), + 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), + 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), + 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), + 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3), + 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3), + 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3), + 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3), + 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3), + #PCS needs to have a sorting index (the number at the end) less than all + #the integer registers which might update the PC. That way if the flag + #bits of the pc state are updated and a branch happens through R15, the + #updates are layered properly and the R15 update isn't lost. + 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0) }}; |