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-rw-r--r--src/arch/arm/isa/operands.isa3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 8e856e74d..3c32d98d1 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -170,6 +170,9 @@ def operands {{
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
+ 'R1': ('IntReg', 'uw', '0', 'IsInteger', 3),
+ 'R2': ('IntReg', 'uw', '1', 'IsInteger', 3),
+ 'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),