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-rw-r--r--src/arch/arm/isa/operands.isa8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index b497564b7..9053f6e92 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -156,10 +156,12 @@ def operands {{
'R3': intRegNPC('3'),
#Pseudo integer condition code registers
- 'CondCodes': intRegCC('INTREG_CONDCODES'),
- 'OptCondCodes': intRegCC(
+ 'CondCodesF': intRegCC('INTREG_CONDCODES_F'),
+ 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'),
+ 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
+ 'OptCondCodesF': intRegCC(
'''(condCode == COND_AL || condCode == COND_UC) ?
- INTREG_ZERO : INTREG_CONDCODES'''),
+ INTREG_ZERO : INTREG_CONDCODES_F'''),
'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
#Abstracted floating point reg operands