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-rw-r--r--src/arch/arm/isa/operands.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 018c0956b..e48c154d4 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -440,6 +440,7 @@ def operands {{
'NextJazelle': pcStateReg('nextJazelle', srtMode),
'NextItState': pcStateReg('nextItstate', srtMode),
'Itstate': pcStateReg('itstate', srtMode),
+ 'NextAArch64': pcStateReg('nextAArch64', srtMode),
#Register operands depending on a field in the instruction encoding. These
#should be avoided since they may not be portable across different