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-rw-r--r--src/arch/arm/isa/operands.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 20ce6df52..49a860213 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -217,7 +217,6 @@ def operands {{
#Fixed index control regs
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
- 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
'Spsr': cntrlRegNC('MISCREG_SPSR'),
'Fpsr': cntrlRegNC('MISCREG_FPSR'),
'Fpsid': cntrlRegNC('MISCREG_FPSID'),
@@ -247,7 +246,8 @@ def operands {{
'Thumb': pcStateReg('thumb', srtPC),
'NextThumb': pcStateReg('nextThumb', srtMode),
'NextJazelle': pcStateReg('nextJazelle', srtMode),
- 'ForcedItState': pcStateReg('forcedItState', srtMode),
+ 'NextItState': pcStateReg('nextItstate', srtMode),
+ 'Itstate': pcStateReg('itstate', srtMode),
#Register operands depending on a field in the instruction encoding. These
#should be avoided since they may not be portable across different