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-rw-r--r--src/arch/arm/isa/operands.isa5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 058cc94f3..a07ee8088 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -169,6 +169,11 @@ def operands {{
'''(condCode == COND_HI || condCode == COND_LS ||
condCode == COND_CS || condCode == COND_CC) ?
INTREG_CONDCODES_C : INTREG_ZERO'''),
+ 'OptShiftRmCondCodesC': intRegCC(
+ '''(condCode == COND_HI || condCode == COND_LS ||
+ condCode == COND_CS || condCode == COND_CC ||
+ shiftType == ROR) ?
+ INTREG_CONDCODES_C : INTREG_ZERO'''),
'OptCondCodesV': intRegCC(
'''(condCode == COND_VS || condCode == COND_VC ||
condCode == COND_GE || condCode == COND_LT ||