diff options
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index a086bb03c..5490a28e0 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -47,6 +47,7 @@ def operand_types {{ 'sw' : ('signed int', 32), 'uw' : ('unsigned int', 32), 'ud' : ('unsigned int', 64), + 'tud' : ('twin64 int', 64), 'sf' : ('float', 32), 'df' : ('float', 64) }}; @@ -96,6 +97,18 @@ def operands {{ 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2), 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2), 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2), + 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2), + 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2), + 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2), + 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2), + 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2), + 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2), + 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2), + 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2), + 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2), + 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2), + 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2), + 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2), 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, maybePCRead, maybePCWrite), 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, @@ -124,6 +137,18 @@ def operands {{ 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2), 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2), 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2), + 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2), + 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2), + 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2), + 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2), + 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2), + 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2), + 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2), + 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2), + 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2), + 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2), + 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2), + 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2), 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, maybePCRead, maybePCWrite), @@ -164,6 +189,7 @@ def operands {{ maybePCRead, maybeIWPCWrite), 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), |